1. Field of the Invention
This invention relates to a digital signal converting apparatus. This invention relates specifically to a signal converting apparatus intended for audio signals superimposed on auxiliary signal areas for video signals as digital signals and capable of reducing its circuit scale upon mutual conversion of the digital audio signals between a component digital video signal format D1 and a composite digital video signal format D2.
2. Description of the Related Art
In video-signal digital series transmission, auxiliary signals can be transmitted utilizing a video flyback or retrace time. When the digital audio signals of these, which are defined by AES/EBU (Audio Engineering Society/European Broadcasting Union), are transmitted using auxiliary signal transmission areas of digital series interfaces (SDI) for a composite digital video signal D2 and a component digital video signal D1, areas for digital audio signals capable of being superimposed on digital video signals have been defined under SMPTE272 standards.
FIG. 4 shows diagonally-shaded signal areas capable of superimposing a composite video signal of a D2 type (4 fsc, 525 lines/60 Hz) thereon. A first field F1 and a second field F2 are illustrated in the same drawing and specific lines for their horizontal and vertical blanking intervals or periods are defined as auxiliary signal areas. The digital audio signal superimposed on each of the auxiliary signal areas will hereinafter be called "composite SDI signal D2".
FIG. 5 shows an example on which a component video signal of a D1 type (4:2:2, 525 lines/60 Hz) is superimposed. A digital audio signal is superimposed on each diagonally-shaded area in the auxiliary signal area. The digital audio signal at this time will be called "component SDI signal D1".
A signal system shown in FIG. 4 is different from that shown in FIG. 5 in auxiliary signal area range. Even in the case of the same lines, they are different from each other in the number of insertable words W. The maximum number of insertable words is represented as shown in the drawing. Only one fields are respectively represented as shown in FIGS. 6A and 6B with audio samples (channels) of inserted audio signals as units.
FIG. 6A shows an example of a component SDI signal D1 and FIG. 6B illustrates an example of a composite SDI signal D2. Even if 1st to 167th lines are the same, they are insertion prohibiting lines or different from each other in the number of data insertable into each line. Therefore, the audio data precisely identical to each other will not be inserted into the lines as shown in the drawing. Thus, the data is distributed to the lines extending up to the 167th line while the lines are being associated with one another. However, the same audio data is inserted into the same lines 168th line or later.
Packet formats of these SDI signals D1 and D2 will now be shown in FIGS. 7 and 8. FIG. 7 shows an example of the packet format for the component SDI signal D1, which consists of audio data and header information arranged in a stage prior to the audio data. The header information consists of four types of headers. ADFs (Ancellary Data Flags) indicate data comprised of three words indicative of the start of each auxiliary signal inserted into a video signal. 000h, 3FFh and 3FFh are used as ADF codes.
A DID (Data Block No) indicates data comprised of one word for identifying the type of audio data, which represents the type of audio group (group 1 to group 4). The audio group is made up of four channels, which are arranged in pairs as in the case of (channel 1 and channel 2) and (channel 3 and channel 4).
A DBN (Data Block Number) indicates a number expressed in one word, which is added to indicate continuity of the audio data within the same channel. As the number, 0 or 1 to 255 are repeated.
A DC (Data Count) indicates the number of words in audio data held within one audio data packet and is comprised of one word.
A CS (Check Sum) indicates data comprised of one word for verifying the effectiveness of audio data and is arranged at the end of the audio data packet.
The audio data consists of three words (respective one words of x, x1 and x2) in a 30-bit configuration. Of these, 20 bits correspond to actual audio data and the remaining bits are comprised of added data (V, U, P and C), a sink flag Z indicative of a start point of an AES audio block, etc.
In the case of the composite SDI signal D2, the ADF consists of one word (3FC). FIG. 8 shows a packet format for the composite SDI signal D2. The composite SDI signal D2 is different from the component SDI signal D1 in that the ADF indicative of the start of the auxiliary signal is made up of one word (code: 3FC) without being comprised of three words and the number of the samples held within the audio data packet is only four (=1 audio group) as distinct from the component SDI signal D1.
In the case of the component SDI signal D2 as shown in FIG. 5, the number of words per line, which can be inserted into each auxiliary signal area, is 268, whereas in the case of the composite SDI signal D1, the number of words per line is 55.
Thus, in order to mutually output the two SDI signals D1 and D2 different from each other in header information and audio packet contents in a state in which their modes or formats have been converted to one another, a signal converting apparatus 10 shown in FIG. 9 is considered to be used.
The signal converting apparatus 10 comprises a first conversion unit 10A and a second conversion unit 10B. An SDI signal D2 supplied to a terminal 12 is converted into a parallel signal represented in the form of 10 bits per word by a serial/parallel converter 14, which in turn is stored in a memory means 16. Therefore, the parallel signal is supplied to a header information discriminator 18 where header information such as a packet start point, determination of an audio group, the number of data words, etc. is detected and determined. Whether or not either type of the SDI signals D1 and D2 is inputted, may refer to an ADF code.
Since a transfer rate of 270 Mbps is used when the composite SDI signal D2 is inputted, a write address generator 20 generates a write clock of 27 MHz. Thus, the composite SDI signal D2 is written into the memory means in accordance with the generated write clock. Data to be written may be written therein only as audio data or may be written inclusive of partial header information. When, on the other hand, the component SDI signal D1 is inputted, its transfer rate is 144 Mbps and hence a write clock and a write address corresponding thereto are generated from the write address generator 20.
A read address generator 22 generates a sampling clock frequency, e.g., 44.1 kHz of audio data. The data stored in the memory means 16 is read out with the sampling clock frequency as a read clock.
The read parallel data is supplied to a second memory means 30 provided within the second conversion unit 10B so that the parallel data is written therein. A clock of 44.1 kHz generated from a write address generator 32 is used as a write clock. Further, a read address generator 34 generates a clock (27 MHz/14.4 MHz) identical to that for the transfer rate (270Mbps or 144 Mbps) to be converted. Memory data is read from the second memory means 30 using the generated clock. At this time, the state of reading of the audio data is controlled so as to make the arrangement of data for the lines shown in FIG. 6.
The read data is supplied to a synthesizer 36. A header information generator 38 generates header information (ADF, DID, etc.) employed in the component SDI signal D1 or the composite SDI signal D2 to be converted. The generated header information is added to the synthesizer 36 to obtain the component SDI signal D1 (and composite SDI signal D2) shown in FIGS. 7 and 8, which in turn is outputted from a terminal 40.
When the signal converting apparatus 10 is now configured as shown in FIG. 9, it is necessary to prepare the memory means 16 and 30 corresponding to the first and second conversion units 10A and 10B respectively. Further, since the read address generator 22 and the write address generator 32 corresponding to these memory means 16 and 30 must be prepared in addition to the above memory means, the signal converting apparatus 10 will result in an increase in its circuit scale and the cost is increased.